1. Field of the Invention
The present invention relates in general to a shift-register circuit. In particular, the present invention relates to a shift-register circuit of a liquid crystal display (LCD) driver.
2. Description of the Related Art
FIG. 1 shows the conventional shift-register circuit disclosed by U.S. Pat. No. 5,410,583 in 1995. Only the single shift-register unit is shown in FIG. 1. The shift-register units connected in serial compose a complete shift-register circuit. In FIG. 1, the input signal is input to the input terminal INPUT and switches the NMOS transistor 12 through the source of the NMOS transistor 10. The output terminal OUTPUT outputs the clock signal C1 when the NMOS transistor 12 is turned on. However, the turned on NMOS transistor 10 acts as a diode, which lowers the voltage level of the signal controlling the NMOS transistor 12.
Clock signal C2 switches the NMOS transistor 14, and the NMOS transistors 14 and 16 are turned on to lower the voltage level of the output terminal OUTPUT when the clock signal C2 is at high voltage level. In addition, the output signal of the next two stage shift-register unit is fed back to the gate of the NMOS transistor 18 to switch the NMOS transistor 18. The voltage level of the gate of the NMOS transistor 12 is lowered quickly when the NMOS transistor 18 is turned on. Thus, the NMOS transistor 12 is turned off and the output terminal stops outputting data.
However, the conventional shift-register circuit requires two clock signals C1 and C2. Thus, the pulse generator must generate more parasitical capacitance, and power consumption is increased. In addition, the layout of the conventional shift-register circuit is complicated because the present shift-register unit is controlled by the next two stage shift-register unit.
The object of the present invention is thus to provide a shift-register circuit comprising a plurality of shift-register units, each inputting a single clock signal, such that the parasitical capacitance at the signal source is decreased. In addition, each shift-register unit receives the output signals from the previous and the next shift-register units. Thus, the circuit layout is simplified.
To achieve the above-mentioned object, the present invention provides a shift-register circuit having a plurality of shift-register units connected in serial for a clock signal, a first voltage, and a second voltage. The first transistor includes a first gate coupled to an output of a previous stage shift-register unit, and a first drain coupled to the first voltage and a first source. The second transistor includes a second gate coupled to an output of a next stage shift-register unit, a second drain coupled to the first source and a second source coupled to the second voltage. The third transistor has a third gate coupled to the second gate, a third drain coupled to the first voltage and a third source. The fourth transistor includes a fourth gate coupled to the first gate, a fourth drain coupled to the third source and a fourth source coupled to the second voltage. The fifth transistor includes a fifth gate coupled to the third source, a fifth drain coupled to a connection point of the first source and the second drain and a fifth source coupled to the second voltage. The sixth transistor includes a sixth gate coupled to the fifth drain, a sixth drain coupled to the clock signal and a sixth source coupled to an output terminal. The seventh transistor includes a seventh gate coupled to the fifth gate, a seventh drain coupled to the output terminal and a seventh source coupled to the second voltage.
In addition, the present invention provides a shift-register circuit having a plurality of shift-register units connected in serial for a clock signal and ground level. The PMOS transistor includes a first gate for receiving an inverted output signal output from an output of a previous stage shift-register unit, a first source for receiving an output signal output from the output of the previous stage shift-register unit and a first drain. The first NMOS transistor includes a second gate coupled to the first drain, a second drain coupled to the clock signal and a second source. The capacitor is coupled between the second gate and the second source. The second NMOS transistor includes a third gate coupled to the first source, a third drain coupled to the second source and a third source coupled to the ground level. The third NMOS transistor includes a fourth gate coupled to an output of a next stage shift-register unit, a fourth drain coupled to a connection point of the second gate and the capacitor and a fourth source coupled to the ground level. The first inverter is coupled to a connection point of the first NMOS transistor and the second NMOS transistor to output an inverted output signal. The second inverter is coupled to the first inverter to output an output signal.